Compensation: The annual base salary range for this position is $127,100 – $203,400.
Location: Ft. Collins, CO

Job Description:

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in
beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS
ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position
offers the opportunity to work on high-performance SoC designs operating at speeds exceeding
1 GHz, from concept through production.

This Floorplanning Engineer role focuses on chip-level physical architecture and integration for
advanced ASICs in deep sub-micron technologies. The position provides hands-on experience
with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout,
including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O
structures for AI, computing, and networking SoCs.

 Define and optimize top-level floorplan architecture, including die size estimation, hierarchy
definition, and partitioning
 Drive macro placement, power grid design, clock distribution planning, pin placement, and
feedthrough optimization
 Collaborate closely with RTL, timing, and packaging teams to balance performance, power,
and area (PPA) targets
 Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean
tapeout readiness
 Coordinate with block owners and integration teams for smooth block-level to top-level
convergence
 Support cross-functional design integration, providing guidance and technical support to
internal and external partners
 Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM
analysis to achieve signoff-quality results
 Contribute to design flow automation and methodology development for advanced process
technologies
 Exercise independent judgment and strong engineering insight in defining methods,
techniques, and evaluation criteria
 Provide technical leadership, mentor others, and lead the execution of new initiatives

Requires:

 BS/MSEE/CE and at least seven (7+) years ASIC design engineering experience with and
emphasis on top-level floor planning
 Strong foundation in VLSI design principles and ASIC physical design fundamentals
 In-depth experience with floorplanning, die partitioning, and hierarchical design
 Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures
 Familiarity with physical verification, DRC/LVS, and congestion/power analysis
 Proven ability to drive PPA optimization through innovative layout and planning strategies
 Strong experience with TCL scripting and Linux environments
 Proficiency in Python, Perl, or Ruby is preferred
 Experience with Cadence or equivalent physical design tools is highly desirable
 Excellent communication, organizational, and problem-solving skills
 Ability to work effectively with customers and cross-functional teams across global sites and
time zones
 Skilled at organizing and presenting large data sets, managing multiple priorities efficiently