Compensation: The annual base salary range for this position is $141,300-226,000
Location: San Jose, CA

Principal Design Verification Engineer

A leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in
SoC and IP development programs. The candidate will be joining a high-performance design team
responsible for state-of-the-art subsystem development to meet customer requirements.

Help develop the verification environment using modern verification techniques (SystemVerilog and
UVM)
Design verification components, including UVM agents and behavioral models
Implement coverage and assertions using System Verilog
Develop random & directed test cases against specifications
Analyze and debug simulation failures
Analyze coverage results

Requires:

 BS/MSEE/CS or equivalent and at least ten (10+) years ASIC design verification experience, verifying
designs at system level and block level
 Fluent knowledge of RTL verification methodologies including System Verilog
 Strong experience in ASIC design verification flows and DV methodologies
 Strong working knowledge of object-oriented verification languages (OVM, UVM, etc.), C/C++, Perl,
and scripting skills
 Strong and independent design debugging capability
 Strong verbal and written communication skills
 Must be comfortable working in a team environment with verification team and design team
members
 Demonstrated ability to analyze and resolve complex verification trade-off scenarios
 Must be a highly productive individual contributor with demonstrated technical capability in system
and sub-block level verification

Desired:

 Experience with hardware design and debug, C++/SystemC and other programming languages
 Experience working with emulators and FPGA-based prototyping
 Familiarity with overall chip design methodologies and tools
 Knowledge of CPU, DDR, bus protocol, network protocol or DSP design