Posted 2 days ago

-Comp: Salary” $180K-$200K, plus full benefits + plus options.

-Visa type: USC, GC, TN, or H1B transfer, Canadian citizen, PR

Location: Boston MA, Montreal, Vancouver or Toronto, Canada

Our Client is a semiconductor company focused on delivering performance leading MEMS timing and frequency reference solutions for the semiconductor industry.

Headquartered in Montreal, our team specializes in MEMS timing products which provides disruptive competitive advantages over quartz-based timing. At Th, we are also passionate about saving time, and reducing system costs for our customers. Our first-to-the-world true dual-output (kHz and MHz) MEMS oscillator replaces two quartz-based oscillators, enabling simplification of system design, miniaturization, BOM reduction, lower current consumption, and lower cost for a variety of applications including wearables, IoT and smartphones.

Our client is transforming the 100-year-old quartz-based timing market to MEMS-based timing with our breakthrough innovation in Timing technology and was the only Canadian company to make it to EE Times Silicon 60: 2018’s Emerging Companies to Watch.


Our client is looking for a Senior ASIC Digital Design Engineer to join our team. We encourage candidates with a strong background in digital design to apply to this position.

The successful candidate will earn valuable experience in a fast moving, collaborative, and high performing Startup environment.

The Senior ASIC Digital Design Engineer will report directly to the Director of ASIC Engineering and will be expected to work a total of 40 hours per week.


  • Develop and implement digital circuits for ASIC projects, ensuring functionality and adherence to design specifications.
  • Perform synthesis and optimization to meet performance, area, and power targets.
  • Coordinate with cross-functional teams for seamless integration of digital designs into larger systems.
  • Prepare comprehensive design documentation, including specifications, test plans, and implementation details.


  • BSEE or MSEE with minimum 3 years’ experience in digital design.
  • Familiar with Verilog and Xcelium. Good knowledge of back-end synthesis tools Genus/Innn Shell, Perl, Python and TCL is a plus.
  • Experience in defining synthesis constraints and STA.
  • Scripting experience, and ability to apply good design quality while meeting tight deadlines.
  • Ability to produce clear and comprehensive design documentation.


  • Understanding of digital logic and verification flow.
  • Experience in synthesis and achieving timing closure.
  • Problem-solving and analytical skills.
  • Works well under pressure and has great time management skills.

Apply Online