Full Time
Winston Salem, NC
Posted 1 day ago
  • Base salary can go to from ~$125K-~$135K
  • Full benefits and relocation.
  • USC, or GC holders

    Job Description:
  • The company is looking for someone who is familiar with digital simulation with digital tools and analog simulation with analog tools and co-simulation of the two together. That is the tricky part of it because most people are either one or the other. A big portion of the job is behavioral modeling of the analog circuits using SystemVerilog, some VerilogA or VerilogAMS modeling as well.  For co-simulation of digital with analog parts, we can do functional stuff on the digital simulator, hence all the behavioral modeling; but at some point, we will do more targeted simulations and we’ll swap out that behavioral model for the real design and then run that simulation.  These things called connect modules, which do the voltage to digital and digital to voltage translation between the two domains and the two different simulators. The simulators are quite helpful and do that automatically for you if the SW guys write the tool properly. In a custom analog environment, it’s useless. There is a lot of control and special case handling of some of that interface between the two simulators to make sure that all the voltage domains are correct, and not some crazy sort of default that the SW guys think up. 
  • Formality is important and we do run that kind of check, but we don’t use format methodologies, as they are for digital verification. The example I have is that if you have an analog circuit that has been designed and it needs some sort of digital assistance for calibration purposes or for temperature modeling or adjusting something, and so you’ve got to simulate the two together while the digital is running and taking a measurement out of the analog, and doing a calculation and feeding back a correction, in this constantly running feedback system; and so you have the digital system computing, and calculating and running in the state machine, and you have this continuous analog thing that is reacting to stimulus and calibration and other stuff. We are building HW so there is lab work involved, too.
  • Our expectation is that we won’t find all these skills but that we will find someone who is strong on one or the other, and we’ll have to train them up.” 
  • They might be able to work full-time remote but will need to be in Winston Salem, NC for a little bit to meet the team and gel with them. 
  • Develop top-down mixed-signal verification strategies for state-of-the-art SoCs, ASICs, and IP blocks containing high-speed digital circuits and sensitive analog/RF circuits.
  • Develop automated test benches and simulation result evaluation tools for top-down block verification.
  • Perform actual verification work using the test benches and strategies developed.
  • Develop tools for automated generation of verification reports and regression management.
  • Integrate and support analog and digital designers developing Verilog-A, behavioral models into full system verification suites.
  • Ensure validity and optimize performance of designer behavioral models.
    • Ensure correct use of connect modules.
  • Work with system architect to develop system tests, stimulating SoC from IC boundary, to ensure functionality with all types of data in all modes of operation.
  • Develop automatic regression of verification suites using Cadence AMS Designer verification flow in Xcelium

  • MSEE/ECE and at least four (4+) years of experience with an analog design flow (e.g. Cadence Virtuoso, Incisive/Xcelium, AMS-Designer, Verilog-AMS and Spectre)
  • Experience with modeling languages: Verilog-A, Verilog-AMS, SystemVerilog/UVM
  • Experience with scripting languages, such as Python, PERL, TCL, BASH/TCSH, etc.
  • Matlab exposure is beneficial.
  • Knowledge creating mixed-signal self-checking test benches that run under automatic regression.
  • Comfort working across both analog and digital design paradigms.
  • Experience verifying ASICs utilizing power gating and multiple clock and power domains is desirable.
  • General understanding of analog circuits and ability to fit analog behavioral models.
  • Self-driven, and able to work independently while coordinating with analog and digital block designer.
  • External applicants must be current US residents with valid US work authorization to be considered.

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